PAPI  5.0.1.0
power5+_events_map.c
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00001 /****************************/
00002 /* THIS IS OPEN SOURCE CODE */
00003 /****************************/
00004 
00005 /*
00006 * File:    power5+_events_map.c
00007 * Author:  Eric Kjeldergaard
00008 *          kjelderg@linux.ibm.com
00009 * Mods:    <your name here>
00010 *          <your email address>
00011 *
00012 * Copyright (c) International Business Machines, 2006.
00013 * Contributed by Eric Kjeldergaard <kjelderg@linux.ibm.com>
00014 *
00015 * This file MUST be kept synchronised with the events file.
00016 *
00017 */
00018 #include "perfctr-ppc64.h"
00019 
00020 PPC64_native_map_t native_name_map[MAX_NATNAME_MAP_INDEX] = {
00021     {"PM_0INST_CLB_CYC", -1}
00022     ,
00023     {"PM_1INST_CLB_CYC", -1}
00024     ,
00025     {"PM_1PLUS_PPC_CMPL", -1}
00026     ,
00027     {"PM_2INST_CLB_CYC", -1}
00028     ,
00029     {"PM_3INST_CLB_CYC", -1}
00030     ,
00031     {"PM_4INST_CLB_CYC", -1}
00032     ,
00033     {"PM_5INST_CLB_CYC", -1}
00034     ,
00035     {"PM_6INST_CLB_CYC", -1}
00036     ,
00037     {"PM_BRQ_FULL_CYC", -1}
00038     ,
00039     {"PM_BR_ISSUED", -1}
00040     ,
00041     {"PM_BR_MPRED_CR", -1}
00042     ,
00043     {"PM_BR_MPRED_TA", -1}
00044     ,
00045     {"PM_BR_UNCOND", -1}
00046     ,
00047     {"PM_CLB_EMPTY_CYC", -1}
00048     ,
00049     {"PM_CLB_FULL_CYC", -1}
00050     ,
00051     {"PM_CRQ_FULL_CYC", -1}
00052     ,
00053     {"PM_CR_MAP_FULL_CYC", -1}
00054     ,
00055     {"PM_CYC", -1}
00056     ,
00057     {"PM_DATA_FROM_L2", -1}
00058     ,
00059     {"PM_DATA_FROM_L25_SHR", -1}
00060     ,
00061     {"PM_DATA_FROM_L275_MOD", -1}
00062     ,
00063     {"PM_DATA_FROM_L3", -1}
00064     ,
00065     {"PM_DATA_FROM_L35_SHR", -1}
00066     ,
00067     {"PM_DATA_FROM_L375_MOD", -1}
00068     ,
00069     {"PM_DATA_FROM_RMEM", -1}
00070     ,
00071     {"PM_DATA_TABLEWALK_CYC", -1}
00072     ,
00073     {"PM_DC_INV_L2", -1}
00074     ,
00075     {"PM_DC_PREF_OUT_OF_STREAMS", -1}
00076     ,
00077     {"PM_DC_PREF_DST", -1}
00078     ,
00079     {"PM_DC_PREF_STREAM_ALLOC", -1}
00080     ,
00081     {"PM_DSLB_MISS", -1}
00082     ,
00083     {"PM_DTLB_MISS", -1}
00084     ,
00085     {"PM_DTLB_MISS_4K", -1}
00086     ,
00087     {"PM_DTLB_REF", -1}
00088     ,
00089     {"PM_DTLB_REF_4K", -1}
00090     ,
00091     {"PM_EE_OFF", -1}
00092     ,
00093     {"PM_EE_OFF_EXT_INT", -1}
00094     ,
00095     {"PM_FAB_CMD_ISSUED", -1}
00096     ,
00097     {"PM_FAB_CMD_RETRIED", -1}
00098     ,
00099     {"PM_FAB_DCLAIM_ISSUED", -1}
00100     ,
00101     {"PM_FAB_DCLAIM_RETRIED", -1}
00102     ,
00103     {"PM_FAB_HOLDtoNN_EMPTY", -1}
00104     ,
00105     {"PM_FAB_HOLDtoVN_EMPTY", -1}
00106     ,
00107     {"PM_FAB_M1toP1_SIDECAR_EMPTY", -1}
00108     ,
00109     {"PM_FAB_M1toVNorNN_SIDECAR_EMPTY", -1}
00110     ,
00111     {"PM_FAB_P1toM1_SIDECAR_EMPTY", -1}
00112     ,
00113     {"PM_FAB_P1toVNorNN_SIDECAR_EMPTY", -1}
00114     ,
00115     {"PM_FAB_PNtoNN_DIRECT", -1}
00116     ,
00117     {"PM_FAB_PNtoNN_SIDECAR", -1}
00118     ,
00119     {"PM_FAB_PNtoVN_DIRECT", -1}
00120     ,
00121     {"PM_FAB_PNtoVN_SIDECAR", -1}
00122     ,
00123     {"PM_FAB_VBYPASS_EMPTY", -1}
00124     ,
00125     {"PM_FLUSH", -1}
00126     ,
00127     {"PM_FLUSH_BR_MPRED", -1}
00128     ,
00129     {"PM_FLUSH_IMBAL", -1}
00130     ,
00131     {"PM_FLUSH_SB", -1}
00132     ,
00133     {"PM_FLUSH_SYNC", -1}
00134     ,
00135     {"PM_FPR_MAP_FULL_CYC", -1}
00136     ,
00137     {"PM_FPU0_1FLOP", -1}
00138     ,
00139     {"PM_FPU0_DENORM", -1}
00140     ,
00141     {"PM_FPU0_FDIV", -1}
00142     ,
00143     {"PM_FPU0_FEST", -1}
00144     ,
00145     {"PM_FPU0_FIN", -1}
00146     ,
00147     {"PM_FPU0_FMA", -1}
00148     ,
00149     {"PM_FPU0_FMOV_FEST", -1}
00150     ,
00151     {"PM_FPU0_FPSCR", -1}
00152     ,
00153     {"PM_FPU0_FRSP_FCONV", -1}
00154     ,
00155     {"PM_FPU0_FSQRT", -1}
00156     ,
00157     {"PM_FPU0_FULL_CYC", -1}
00158     ,
00159     {"PM_FPU0_SINGLE", -1}
00160     ,
00161     {"PM_FPU0_STALL3", -1}
00162     ,
00163     {"PM_FPU0_STF", -1}
00164     ,
00165     {"PM_FPU1_1FLOP", -1}
00166     ,
00167     {"PM_FPU1_DENORM", -1}
00168     ,
00169     {"PM_FPU1_FDIV", -1}
00170     ,
00171     {"PM_FPU1_FEST", -1}
00172     ,
00173     {"PM_FPU1_FIN", -1}
00174     ,
00175     {"PM_FPU1_FMA", -1}
00176     ,
00177     {"PM_FPU1_FMOV_FEST", -1}
00178     ,
00179     {"PM_FPU1_FRSP_FCONV", -1}
00180     ,
00181     {"PM_FPU1_FSQRT", -1}
00182     ,
00183     {"PM_FPU1_FULL_CYC", -1}
00184     ,
00185     {"PM_FPU1_SINGLE", -1}
00186     ,
00187     {"PM_FPU1_STALL3", -1}
00188     ,
00189     {"PM_FPU1_STF", -1}
00190     ,
00191     {"PM_FPU_1FLOP", -1}
00192     ,
00193     {"PM_FPU_DENORM", -1}
00194     ,
00195     {"PM_FPU_FDIV", -1}
00196     ,
00197     {"PM_FPU_FEST", -1}
00198     ,
00199     {"PM_FPU_FULL_CYC", -1}
00200     ,
00201     {"PM_FPU_SINGLE", -1}
00202     ,
00203     {"PM_FXLS0_FULL_CYC", -1}
00204     ,
00205     {"PM_FXLS1_FULL_CYC", -1}
00206     ,
00207     {"PM_FXLS_FULL_CYC", -1}
00208     ,
00209     {"PM_FXU0_FIN", -1}
00210     ,
00211     {"PM_FXU1_FIN", -1}
00212     ,
00213     {"PM_FXU_IDLE", -1}
00214     ,
00215     {"PM_GCT_FULL_CYC", -1}
00216     ,
00217     {"PM_GCT_NOSLOT_CYC", -1}
00218     ,
00219     {"PM_GCT_USAGE_00to59_CYC", -1}
00220     ,
00221     {"PM_GPR_MAP_FULL_CYC", -1}
00222     ,
00223     {"PM_GRP_BR_REDIR", -1}
00224     ,
00225     {"PM_GRP_BR_REDIR_NONSPEC", -1}
00226     ,
00227     {"PM_GRP_DISP_BLK_SB_CYC", -1}
00228     ,
00229     {"PM_GRP_DISP_REJECT", -1}
00230     ,
00231     {"PM_GRP_DISP_VALID", -1}
00232     ,
00233     {"PM_GRP_IC_MISS", -1}
00234     ,
00235     {"PM_GRP_IC_MISS_BR_REDIR_NONSPEC", -1}
00236     ,
00237     {"PM_GRP_IC_MISS_NONSPEC", -1}
00238     ,
00239     {"PM_GRP_MRK", -1}
00240     ,
00241     {"PM_IC_DEMAND_L2_BHT_REDIRECT", -1}
00242     ,
00243     {"PM_IC_DEMAND_L2_BR_REDIRECT", -1}
00244     ,
00245     {"PM_IC_PREF_REQ", -1}
00246     ,
00247     {"PM_IERAT_XLATE_WR", -1}
00248     ,
00249     {"PM_IERAT_XLATE_WR_LP", -1}
00250     ,
00251     {"PM_IOPS_CMPL", -1}
00252     ,
00253     {"PM_INST_DISP_ATTEMPT", -1}
00254     ,
00255     {"PM_INST_FETCH_CYC", -1}
00256     ,
00257     {"PM_INST_FROM_L2", -1}
00258     ,
00259     {"PM_INST_FROM_L25_SHR", -1}
00260     ,
00261     {"PM_INST_FROM_L2MISS", -1}
00262     ,
00263     {"PM_INST_FROM_L3", -1}
00264     ,
00265     {"PM_INST_FROM_L35_SHR", -1}
00266     ,
00267     {"PM_ISLB_MISS", -1}
00268     ,
00269     {"PM_ITLB_MISS", -1}
00270     ,
00271     {"PM_L1_DCACHE_RELOAD_VALID", -1}
00272     ,
00273     {"PM_L1_PREF", -1}
00274     ,
00275     {"PM_L1_WRITE_CYC", -1}
00276     ,
00277     {"PM_L2SA_MOD_INV", -1}
00278     ,
00279     {"PM_L2SA_MOD_TAG", -1}
00280     ,
00281     {"PM_L2SA_RCLD_DISP", -1}
00282     ,
00283     {"PM_L2SA_RCLD_DISP_FAIL_ADDR", -1}
00284     ,
00285     {"PM_L2SA_RCLD_DISP_FAIL_OTHER", -1}
00286     ,
00287     {"PM_L2SA_RCLD_DISP_FAIL_RC_FULL", -1}
00288     ,
00289     {"PM_L2SA_RCST_DISP", -1}
00290     ,
00291     {"PM_L2SA_RCST_DISP_FAIL_ADDR", -1}
00292     ,
00293     {"PM_L2SA_RCST_DISP_FAIL_OTHER", -1}
00294     ,
00295     {"PM_L2SA_RCST_DISP_FAIL_RC_FULL", -1}
00296     ,
00297     {"PM_L2SA_RC_DISP_FAIL_CO_BUSY", -1}
00298     ,
00299     {"PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL", -1}
00300     ,
00301     {"PM_L2SA_SHR_INV", -1}
00302     ,
00303     {"PM_L2SA_SHR_MOD", -1}
00304     ,
00305     {"PM_L2SA_ST_HIT", -1}
00306     ,
00307     {"PM_L2SA_ST_REQ", -1}
00308     ,
00309     {"PM_L2SB_MOD_INV", -1}
00310     ,
00311     {"PM_L2SB_MOD_TAG", -1}
00312     ,
00313     {"PM_L2SB_RCLD_DISP", -1}
00314     ,
00315     {"PM_L2SB_RCLD_DISP_FAIL_ADDR", -1}
00316     ,
00317     {"PM_L2SB_RCLD_DISP_FAIL_OTHER", -1}
00318     ,
00319     {"PM_L2SB_RCLD_DISP_FAIL_RC_FULL", -1}
00320     ,
00321     {"PM_L2SB_RCST_DISP", -1}
00322     ,
00323     {"PM_L2SB_RCST_DISP_FAIL_ADDR", -1}
00324     ,
00325     {"PM_L2SB_RCST_DISP_FAIL_OTHER", -1}
00326     ,
00327     {"PM_L2SB_RCST_DISP_FAIL_RC_FULL", -1}
00328     ,
00329     {"PM_L2SB_RC_DISP_FAIL_CO_BUSY", -1}
00330     ,
00331     {"PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL", -1}
00332     ,
00333     {"PM_L2SB_SHR_INV", -1}
00334     ,
00335     {"PM_L2SB_SHR_MOD", -1}
00336     ,
00337     {"PM_L2SB_ST_HIT", -1}
00338     ,
00339     {"PM_L2SB_ST_REQ", -1}
00340     ,
00341     {"PM_L2SC_MOD_INV", -1}
00342     ,
00343     {"PM_L2SC_MOD_TAG", -1}
00344     ,
00345     {"PM_L2SC_RCLD_DISP", -1}
00346     ,
00347     {"PM_L2SC_RCLD_DISP_FAIL_ADDR", -1}
00348     ,
00349     {"PM_L2SC_RCLD_DISP_FAIL_OTHER", -1}
00350     ,
00351     {"PM_L2SC_RCLD_DISP_FAIL_RC_FULL", -1}
00352     ,
00353     {"PM_L2SC_RCST_DISP", -1}
00354     ,
00355     {"PM_L2SC_RCST_DISP_FAIL_ADDR", -1}
00356     ,
00357     {"PM_L2SC_RCST_DISP_FAIL_OTHER", -1}
00358     ,
00359     {"PM_L2SC_RCST_DISP_FAIL_RC_FULL", -1}
00360     ,
00361     {"PM_L2SC_RC_DISP_FAIL_CO_BUSY", -1}
00362     ,
00363     {"PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL", -1}
00364     ,
00365     {"PM_L2SC_SHR_INV", -1}
00366     ,
00367     {"PM_L2SC_SHR_MOD", -1}
00368     ,
00369     {"PM_L2SC_ST_HIT", -1}
00370     ,
00371     {"PM_L2SC_ST_REQ", -1}
00372     ,
00373     {"PM_L2_PREF", -1}
00374     ,
00375     {"PM_L3SA_ALL_BUSY", -1}
00376     ,
00377     {"PM_L3SA_HIT", -1}
00378     ,
00379     {"PM_L3SA_MOD_INV", -1}
00380     ,
00381     {"PM_L3SA_MOD_TAG", -1}
00382     ,
00383     {"PM_L3SA_REF", -1}
00384     ,
00385     {"PM_L3SA_SHR_INV", -1}
00386     ,
00387     {"PM_L3SA_SNOOP_RETRY", -1}
00388     ,
00389     {"PM_L3SB_ALL_BUSY", -1}
00390     ,
00391     {"PM_L3SB_HIT", -1}
00392     ,
00393     {"PM_L3SB_MOD_INV", -1}
00394     ,
00395     {"PM_L3SB_MOD_TAG", -1}
00396     ,
00397     {"PM_L3SB_REF", -1}
00398     ,
00399     {"PM_L3SB_SHR_INV", -1}
00400     ,
00401     {"PM_L3SB_SNOOP_RETRY", -1}
00402     ,
00403     {"PM_L3SC_ALL_BUSY", -1}
00404     ,
00405     {"PM_L3SC_HIT", -1}
00406     ,
00407     {"PM_L3SC_MOD_INV", -1}
00408     ,
00409     {"PM_L3SC_MOD_TAG", -1}
00410     ,
00411     {"PM_L3SC_REF", -1}
00412     ,
00413     {"PM_L3SC_SHR_INV", -1}
00414     ,
00415     {"PM_L3SC_SNOOP_RETRY", -1}
00416     ,
00417     {"PM_LARX_LSU0", -1}
00418     ,
00419     {"PM_LD_MISS_L1_LSU0", -1}
00420     ,
00421     {"PM_LD_MISS_L1_LSU1", -1}
00422     ,
00423     {"PM_LD_REF_L1", -1}
00424     ,
00425     {"PM_LD_REF_L1_LSU0", -1}
00426     ,
00427     {"PM_BR_PRED_TA", -1}
00428     ,
00429     {"PM_LR_CTR_MAP_FULL_CYC", -1}
00430     ,
00431     {"PM_LSU0_BUSY_REJECT", -1}
00432     ,
00433     {"PM_LSU0_DERAT_MISS", -1}
00434     ,
00435     {"PM_LSU0_FLUSH_LRQ", -1}
00436     ,
00437     {"PM_LSU0_FLUSH_SRQ", -1}
00438     ,
00439     {"PM_LSU0_FLUSH_ULD", -1}
00440     ,
00441     {"PM_LSU0_FLUSH_UST", -1}
00442     ,
00443     {"PM_LSU0_LDF", -1}
00444     ,
00445     {"PM_LSU0_NCLD", -1}
00446     ,
00447     {"PM_LSU0_REJECT_ERAT_MISS", -1}
00448     ,
00449     {"PM_LSU0_REJECT_LMQ_FULL", -1}
00450     ,
00451     {"PM_LSU0_REJECT_RELOAD_CDF", -1}
00452     ,
00453     {"PM_LSU0_REJECT_SRQ", -1}
00454     ,
00455     {"PM_LSU0_SRQ_STFWD", -1}
00456     ,
00457     {"PM_LSU1_BUSY_REJECT", -1}
00458     ,
00459     {"PM_LSU1_DERAT_MISS", -1}
00460     ,
00461     {"PM_LSU1_FLUSH_LRQ", -1}
00462     ,
00463     {"PM_LSU1_FLUSH_SRQ", -1}
00464     ,
00465     {"PM_LSU1_FLUSH_ULD", -1}
00466     ,
00467     {"PM_LSU1_FLUSH_UST", -1}
00468     ,
00469     {"PM_LSU1_LDF", -1}
00470     ,
00471     {"PM_LSU1_NCLD", -1}
00472     ,
00473     {"PM_LSU1_REJECT_ERAT_MISS", -1}
00474     ,
00475     {"PM_LSU1_REJECT_LMQ_FULL", -1}
00476     ,
00477     {"PM_LSU1_REJECT_RELOAD_CDF", -1}
00478     ,
00479     {"PM_LSU1_REJECT_SRQ", -1}
00480     ,
00481     {"PM_LSU1_SRQ_STFWD", -1}
00482     ,
00483     {"PM_LSU_FLUSH", -1}
00484     ,
00485     {"PM_LSU_FLUSH_LRQ_FULL", -1}
00486     ,
00487     {"PM_LSU_FLUSH_SRQ", -1}
00488     ,
00489     {"PM_LSU_FLUSH_SRQ_FULL", -1}
00490     ,
00491     {"PM_LSU_FLUSH_ULD", -1}
00492     ,
00493     {"PM_LSU_LDF", -1}
00494     ,
00495     {"PM_LSU_LMQ_FULL_CYC", -1}
00496     ,
00497     {"PM_LSU_LMQ_LHR_MERGE", -1}
00498     ,
00499     {"PM_LSU_LMQ_S0_ALLOC", -1}
00500     ,
00501     {"PM_LSU_LMQ_S0_VALID", -1}
00502     ,
00503     {"PM_LSU_LRQ_FULL_CYC", -1}
00504     ,
00505     {"PM_LSU_LRQ_S0_ALLOC", -1}
00506     ,
00507     {"PM_LSU_LRQ_S0_VALID", -1}
00508     ,
00509     {"PM_LSU_REJECT_ERAT_MISS", -1}
00510     ,
00511     {"PM_LSU_REJECT_SRQ", -1}
00512     ,
00513     {"PM_LSU_SRQ_FULL_CYC", -1}
00514     ,
00515     {"PM_LSU_SRQ_S0_ALLOC", -1}
00516     ,
00517     {"PM_LSU_SRQ_S0_VALID", -1}
00518     ,
00519     {"PM_LSU_SRQ_SYNC_CYC", -1}
00520     ,
00521     {"PM_LWSYNC_HELD", -1}
00522     ,
00523     {"PM_MEM_FAST_PATH_RD_DISP", -1}
00524     ,
00525     {"PM_IC_PREF_INSTALL", -1}
00526     ,
00527     {"PM_MEM_HI_PRIO_WR_CMPL", -1}
00528     ,
00529     {"PM_MEM_NONSPEC_RD_CANCEL", -1}
00530     ,
00531     {"PM_MEM_LO_PRIO_WR_CMPL", -1}
00532     ,
00533     {"PM_MEM_PWQ_DISP", -1}
00534     ,
00535     {"PM_MEM_PWQ_DISP_Q2or3", -1}
00536     ,
00537     {"PM_MEM_PW_CMPL", -1}
00538     ,
00539     {"PM_MEM_PW_GATH", -1}
00540     ,
00541     {"PM_MEM_RQ_DISP_Q0to3", -1}
00542     ,
00543     {"PM_MEM_RQ_DISP", -1}
00544     ,
00545     {"PM_MEM_RQ_DISP_Q4to7", -1}
00546     ,
00547     {"PM_MEM_RQ_DISP_Q8to11", -1}
00548     ,
00549     {"PM_MEM_SPEC_RD_CANCEL", -1}
00550     ,
00551     {"PM_MEM_WQ_DISP_Q0to7", -1}
00552     ,
00553     {"PM_MEM_WQ_DISP_Q8to15", -1}
00554     ,
00555     {"PM_MEM_WQ_DISP_DCLAIM", -1}
00556     ,
00557     {"PM_MEM_WQ_DISP_WRITE", -1}
00558     ,
00559     {"PM_MRK_DATA_FROM_L2", -1}
00560     ,
00561     {"PM_MRK_DATA_FROM_L25_SHR", -1}
00562     ,
00563     {"PM_MRK_DATA_FROM_L275_MOD", -1}
00564     ,
00565     {"PM_MRK_DATA_FROM_L3", -1}
00566     ,
00567     {"PM_MRK_DATA_FROM_L35_SHR", -1}
00568     ,
00569     {"PM_MRK_DATA_FROM_L375_MOD", -1}
00570     ,
00571     {"PM_MRK_DATA_FROM_RMEM", -1}
00572     ,
00573     {"PM_MRK_DSLB_MISS", -1}
00574     ,
00575     {"PM_MRK_DTLB_MISS", -1}
00576     ,
00577     {"PM_MRK_DTLB_MISS_4K", -1}
00578     ,
00579     {"PM_MRK_DTLB_REF", -1}
00580     ,
00581     {"PM_MRK_DTLB_REF_4K", -1}
00582     ,
00583     {"PM_MRK_GRP_DISP", -1}
00584     ,
00585     {"PM_MRK_GRP_ISSUED", -1}
00586     ,
00587     {"PM_MRK_IMR_RELOAD", -1}
00588     ,
00589     {"PM_MRK_L1_RELOAD_VALID", -1}
00590     ,
00591     {"PM_MRK_LD_MISS_L1", -1}
00592     ,
00593     {"PM_MRK_LD_MISS_L1_LSU0", -1}
00594     ,
00595     {"PM_MRK_LD_MISS_L1_LSU1", -1}
00596     ,
00597     {"PM_MRK_LSU0_FLUSH_LRQ", -1}
00598     ,
00599     {"PM_MRK_LSU0_FLUSH_SRQ", -1}
00600     ,
00601     {"PM_MRK_LSU0_FLUSH_ULD", -1}
00602     ,
00603     {"PM_MRK_LSU0_FLUSH_UST", -1}
00604     ,
00605     {"PM_MRK_LSU1_FLUSH_LRQ", -1}
00606     ,
00607     {"PM_MRK_LSU1_FLUSH_SRQ", -1}
00608     ,
00609     {"PM_MRK_LSU1_FLUSH_ULD", -1}
00610     ,
00611     {"PM_MRK_LSU1_FLUSH_UST", -1}
00612     ,
00613     {"PM_MRK_LSU_FLUSH_ULD", -1}
00614     ,
00615     {"PM_MRK_LSU_SRQ_INST_VALID", -1}
00616     ,
00617     {"PM_MRK_STCX_FAIL", -1}
00618     ,
00619     {"PM_MRK_ST_CMPL", -1}
00620     ,
00621     {"PM_MRK_ST_MISS_L1", -1}
00622     ,
00623     {"PM_PMC4_OVERFLOW", -1}
00624     ,
00625     {"PM_PMC5_OVERFLOW", -1}
00626     ,
00627     {"PM_INST_CMPL", -1}
00628     ,
00629     {"PM_PTEG_FROM_L2", -1}
00630     ,
00631     {"PM_PTEG_FROM_L25_SHR", -1}
00632     ,
00633     {"PM_PTEG_FROM_L275_MOD", -1}
00634     ,
00635     {"PM_PTEG_FROM_L3", -1}
00636     ,
00637     {"PM_PTEG_FROM_L35_SHR", -1}
00638     ,
00639     {"PM_PTEG_FROM_L375_MOD", -1}
00640     ,
00641     {"PM_PTEG_FROM_RMEM", -1}
00642     ,
00643     {"PM_PTEG_RELOAD_VALID", -1}
00644     ,
00645     {"PM_RUN_CYC", -1}
00646     ,
00647     {"PM_SNOOP_DCLAIM_RETRY_QFULL", -1}
00648     ,
00649     {"PM_SNOOP_PARTIAL_RTRY_QFULL", -1}
00650     ,
00651     {"PM_SNOOP_PW_RETRY_RQ", -1}
00652     ,
00653     {"PM_SNOOP_PW_RETRY_WQ_PWQ", -1}
00654     ,
00655     {"PM_SNOOP_RD_RETRY_QFULL", -1}
00656     ,
00657     {"PM_SNOOP_RD_RETRY_RQ", -1}
00658     ,
00659     {"PM_SNOOP_RD_RETRY_WQ", -1}
00660     ,
00661     {"PM_SNOOP_RETRY_1AHEAD", -1}
00662     ,
00663     {"PM_SNOOP_TLBIE", -1}
00664     ,
00665     {"PM_SNOOP_WR_RETRY_QFULL", -1}
00666     ,
00667     {"PM_SNOOP_WR_RETRY_RQ", -1}
00668     ,
00669     {"PM_SNOOP_WR_RETRY_WQ", -1}
00670     ,
00671     {"PM_STCX_FAIL", -1}
00672     ,
00673     {"PM_STCX_PASS", -1}
00674     ,
00675     {"PM_ST_MISS_L1", -1}
00676     ,
00677     {"PM_ST_REF_L1_LSU0", -1}
00678     ,
00679     {"PM_ST_REF_L1_LSU1", -1}
00680     ,
00681     {"PM_SUSPENDED", -1}
00682     ,
00683     {"PM_TB_BIT_TRANS", -1}
00684     ,
00685     {"PM_THRD_L2MISS_BOTH_CYC", -1}
00686     ,
00687     {"PM_THRD_ONE_RUN_CYC", -1}
00688     ,
00689     {"PM_THRD_PRIO_1_CYC", -1}
00690     ,
00691     {"PM_THRD_PRIO_2_CYC", -1}
00692     ,
00693     {"PM_THRD_PRIO_3_CYC", -1}
00694     ,
00695     {"PM_THRD_PRIO_4_CYC", -1}
00696     ,
00697     {"PM_THRD_PRIO_5_CYC", -1}
00698     ,
00699     {"PM_THRD_PRIO_6_CYC", -1}
00700     ,
00701     {"PM_THRD_PRIO_7_CYC", -1}
00702     ,
00703     {"PM_THRD_PRIO_DIFF_0_CYC", -1}
00704     ,
00705     {"PM_THRD_PRIO_DIFF_1or2_CYC", -1}
00706     ,
00707     {"PM_THRD_PRIO_DIFF_3or4_CYC", -1}
00708     ,
00709     {"PM_THRD_PRIO_DIFF_5or6_CYC", -1}
00710     ,
00711     {"PM_THRD_PRIO_DIFF_minus1or2_CYC", -1}
00712     ,
00713     {"PM_THRD_PRIO_DIFF_minus3or4_CYC", -1}
00714     ,
00715     {"PM_THRD_PRIO_DIFF_minus5or6_CYC", -1}
00716     ,
00717     {"PM_THRD_SEL_OVER_CLB_EMPTY", -1}
00718     ,
00719     {"PM_THRD_SEL_OVER_GCT_IMBAL", -1}
00720     ,
00721     {"PM_THRD_SEL_OVER_ISU_HOLD", -1}
00722     ,
00723     {"PM_THRD_SEL_OVER_L2MISS", -1}
00724     ,
00725     {"PM_THRD_SEL_T0", -1}
00726     ,
00727     {"PM_THRD_SEL_T1", -1}
00728     ,
00729     {"PM_THRD_SMT_HANG", -1}
00730     ,
00731     {"PM_TLBIE_HELD", -1}
00732     ,
00733     {"PM_TLB_MISS", -1}
00734     ,
00735     {"PM_XER_MAP_FULL_CYC", -1}
00736     ,
00737     {"PM_BR_PRED_CR", -1}
00738     ,
00739     {"PM_MEM_RQ_DISP_Q12to15", -1}
00740     ,
00741     {"PM_MEM_RQ_DISP_Q16to19", -1}
00742     ,
00743     {"PM_SNOOP_RETRY_AB_COLLISION", -1}
00744     ,
00745     {"PM_CMPLU_STALL_DCACHE_MISS", -1}
00746     ,
00747     {"PM_CMPLU_STALL_FDIV", -1}
00748     ,
00749     {"PM_CMPLU_STALL_FXU", -1}
00750     ,
00751     {"PM_CMPLU_STALL_LSU", -1}
00752     ,
00753     {"PM_DATA_FROM_L25_MOD", -1}
00754     ,
00755     {"PM_DATA_FROM_L35_MOD", -1}
00756     ,
00757     {"PM_DATA_FROM_LMEM", -1}
00758     ,
00759     {"PM_DTLB_MISS_64K", -1}
00760     ,
00761     {"PM_DTLB_REF_64K", -1}
00762     ,
00763     {"PM_FPU_FMA", -1}
00764     ,
00765     {"PM_FPU_FRSP_FCONV", -1}
00766     ,
00767     {"PM_FPU_FSQRT", -1}
00768     ,
00769     {"PM_FPU_STALL3", -1}
00770     ,
00771     {"PM_FPU_STF", -1}
00772     ,
00773     {"PM_FXU_BUSY", -1}
00774     ,
00775     {"PM_MRK_FXU_FIN", -1}
00776     ,
00777     {"PM_GCT_EMPTY_CYC", -1}
00778     ,
00779     {"PM_GCT_NOSLOT_IC_MISS", -1}
00780     ,
00781     {"PM_GCT_USAGE_60to79_CYC", -1}
00782     ,
00783     {"PM_GRP_DISP", -1}
00784     ,
00785     {"PM_HV_CYC", -1}
00786     ,
00787     {"PM_INST_FROM_L1", -1}
00788     ,
00789     {"PM_INST_FROM_L25_MOD", -1}
00790     ,
00791     {"PM_INST_FROM_L35_MOD", -1}
00792     ,
00793     {"PM_INST_FROM_LMEM", -1}
00794     ,
00795     {"PM_LSU_BUSY_REJECT", -1}
00796     ,
00797     {"PM_LSU_DERAT_MISS", -1}
00798     ,
00799     {"PM_LSU_FLUSH_LRQ", -1}
00800     ,
00801     {"PM_LSU_FLUSH_UST", -1}
00802     ,
00803     {"PM_LSU_LMQ_SRQ_EMPTY_CYC", -1}
00804     ,
00805     {"PM_LSU_REJECT_LMQ_FULL", -1}
00806     ,
00807     {"PM_LSU_REJECT_RELOAD_CDF", -1}
00808     ,
00809     {"PM_LSU_SRQ_STFWD", -1}
00810     ,
00811     {"PM_MRK_BRU_FIN", -1}
00812     ,
00813     {"PM_MRK_DATA_FROM_L25_MOD", -1}
00814     ,
00815     {"PM_MRK_DATA_FROM_L25_SHR_CYC", -1}
00816     ,
00817     {"PM_MRK_DATA_FROM_L275_SHR_CYC", -1}
00818     ,
00819     {"PM_MRK_DATA_FROM_L2_CYC", -1}
00820     ,
00821     {"PM_MRK_DATA_FROM_L35_MOD", -1}
00822     ,
00823     {"PM_MRK_DATA_FROM_L35_SHR_CYC", -1}
00824     ,
00825     {"PM_MRK_DATA_FROM_L375_SHR_CYC", -1}
00826     ,
00827     {"PM_MRK_DATA_FROM_L3_CYC", -1}
00828     ,
00829     {"PM_MRK_DATA_FROM_LMEM", -1}
00830     ,
00831     {"PM_MRK_DTLB_MISS_64K", -1}
00832     ,
00833     {"PM_MRK_DTLB_REF_64K", -1}
00834     ,
00835     {"PM_MRK_GRP_BR_REDIR", -1}
00836     ,
00837     {"PM_MRK_LSU_FLUSH_UST", -1}
00838     ,
00839     {"PM_MRK_ST_GPS", -1}
00840     ,
00841     {"PM_PMC1_OVERFLOW", -1}
00842     ,
00843     {"PM_PTEG_FROM_L25_MOD", -1}
00844     ,
00845     {"PM_PTEG_FROM_L35_MOD", -1}
00846     ,
00847     {"PM_PTEG_FROM_LMEM", -1}
00848     ,
00849     {"PM_SLB_MISS", -1}
00850     ,
00851     {"PM_ST_REF_L1", -1}
00852     ,
00853     {"PM_THRD_GRP_CMPL_BOTH_CYC", -1}
00854     ,
00855     {"PM_DATA_FROM_L275_SHR", -1}
00856     ,
00857     {"PM_DATA_FROM_L2MISS", -1}
00858     ,
00859     {"PM_DATA_FROM_L375_SHR", -1}
00860     ,
00861     {"PM_DTLB_MISS_16M", -1}
00862     ,
00863     {"PM_DTLB_REF_16M", -1}
00864     ,
00865     {"PM_FPU_FMOV_FEST", -1}
00866     ,
00867     {"PM_FXU0_BUSY_FXU1_IDLE", -1}
00868     ,
00869     {"PM_FXU_FIN", -1}
00870     ,
00871     {"PM_GCT_NOSLOT_SRQ_FULL", -1}
00872     ,
00873     {"PM_GCT_USAGE_80to99_CYC", -1}
00874     ,
00875     {"PM_GRP_CMPL", -1}
00876     ,
00877     {"PM_GRP_DISP_SUCCESS", -1}
00878     ,
00879     {"PM_INST_DISP", -1}
00880     ,
00881     {"PM_INST_FROM_L275_SHR", -1}
00882     ,
00883     {"PM_INST_FROM_L375_SHR", -1}
00884     ,
00885     {"PM_INST_FROM_PREF", -1}
00886     ,
00887     {"PM_LD_MISS_L1", -1}
00888     ,
00889     {"PM_MRK_DATA_FROM_L275_SHR", -1}
00890     ,
00891     {"PM_MRK_DATA_FROM_L2MISS", -1}
00892     ,
00893     {"PM_MRK_DATA_FROM_L375_SHR", -1}
00894     ,
00895     {"PM_MRK_DTLB_MISS_16M", -1}
00896     ,
00897     {"PM_MRK_DTLB_REF_16M", -1}
00898     ,
00899     {"PM_MRK_FPU_FIN", -1}
00900     ,
00901     {"PM_MRK_INST_FIN", -1}
00902     ,
00903     {"PM_MRK_LSU_FLUSH_LRQ", -1}
00904     ,
00905     {"PM_MRK_ST_CMPL_INT", -1}
00906     ,
00907     {"PM_PMC2_OVERFLOW", -1}
00908     ,
00909     {"PM_PMC6_OVERFLOW", -1}
00910     ,
00911     {"PM_PTEG_FROM_L275_SHR", -1}
00912     ,
00913     {"PM_PTEG_FROM_L2MISS", -1}
00914     ,
00915     {"PM_PTEG_FROM_L375_SHR", -1}
00916     ,
00917     {"PM_STOP_COMPLETION", -1}
00918     ,
00919     {"PM_THRESH_TIMEO", -1}
00920     ,
00921     {"PM_0INST_FETCH", -1}
00922     ,
00923     {"PM_BR_PRED_CR_TA", -1}
00924     ,
00925     {"PM_CMPLU_STALL_DIV", -1}
00926     ,
00927     {"PM_CMPLU_STALL_ERAT_MISS", -1}
00928     ,
00929     {"PM_CMPLU_STALL_FPU", -1}
00930     ,
00931     {"PM_CMPLU_STALL_REJECT", -1}
00932     ,
00933     {"PM_DTLB_MISS_16G", -1}
00934     ,
00935     {"PM_DTLB_REF_16G", -1}
00936     ,
00937     {"PM_EXT_INT", -1}
00938     ,
00939     {"PM_FPU_FIN", -1}
00940     ,
00941     {"PM_FXU1_BUSY_FXU0_IDLE", -1}
00942     ,
00943     {"PM_GCT_NOSLOT_BR_MPRED", -1}
00944     ,
00945     {"PM_INST_FROM_L275_MOD", -1}
00946     ,
00947     {"PM_INST_FROM_L375_MOD", -1}
00948     ,
00949     {"PM_INST_FROM_RMEM", -1}
00950     ,
00951     {"PM_LSU_SRQ_EMPTY_CYC", -1}
00952     ,
00953     {"PM_MRK_CRU_FIN", -1}
00954     ,
00955     {"PM_MRK_DATA_FROM_L25_MOD_CYC", -1}
00956     ,
00957     {"PM_MRK_DATA_FROM_L275_MOD_CYC", -1}
00958     ,
00959     {"PM_MRK_DATA_FROM_L35_MOD_CYC", -1}
00960     ,
00961     {"PM_MRK_DATA_FROM_L375_MOD_CYC", -1}
00962     ,
00963     {"PM_MRK_DATA_FROM_LMEM_CYC", -1}
00964     ,
00965     {"PM_MRK_DATA_FROM_RMEM_CYC", -1}
00966     ,
00967     {"PM_MRK_DTLB_MISS_16G", -1}
00968     ,
00969     {"PM_MRK_DTLB_REF_16G", -1}
00970     ,
00971     {"PM_MRK_GRP_CMPL", -1}
00972     ,
00973     {"PM_MRK_GRP_IC_MISS", -1}
00974     ,
00975     {"PM_MRK_GRP_TIMEO", -1}
00976     ,
00977     {"PM_MRK_LSU_FIN", -1}
00978     ,
00979     {"PM_MRK_LSU_FLUSH_SRQ", -1}
00980     ,
00981     {"PM_PMC3_OVERFLOW", -1}
00982     ,
00983     {"PM_WORK_HELD", -1}
00984     ,
00985     {"PM_RUN_INST_CMPL", -1}
00986 };
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