d9/d5c/ppc970__events__map_8c_source.html

00001 /****************************/
00002 /* THIS IS OPEN SOURCE CODE */
00003 /****************************/
00004
00005 /*
00006 * File:    ppc970_events_map.c
00007 * Author:  Maynard Johnson
00008 *          maynardj@us.ibm.com
00009 * Mods:    <your name here>
00010 *          <your email address>
00011 *
00012 * This file MUST be kept synchronised with the events file.
00013 *
00014 */
00015 #include "perfctr-ppc64.h"
00016
00017 PPC64_native_map_t native_name_map[MAX_NATNAME_MAP_INDEX] = {
00018     {"PM_BRQ_FULL_CYC", -1}
00019     ,
00020     {"PM_CR_MAP_FULL_CYC", -1}
00021     ,
00022     {"PM_CYC", -1}
00023     ,
00024     {"PM_DATA_FROM_L2", -1}
00025     ,
00026     {"PM_DATA_TABLEWALK_CYC", -1}
00027     ,
00028     {"PM_DSLB_MISS", -1}
00029     ,
00030     {"PM_DTLB_MISS", -1}
00031     ,
00032     {"PM_FPR_MAP_FULL_CYC", -1}
00033     ,
00034     {"PM_FPU0_ALL", -1}
00035     ,
00036     {"PM_FPU0_DENORM", -1}
00037     ,
00038     {"PM_FPU0_FDIV", -1}
00039     ,
00040     {"PM_FPU0_FMA", -1}
00041     ,
00042     {"PM_FPU0_FSQRT", -1}
00043     ,
00044     {"PM_FPU0_FULL_CYC", -1}
00045     ,
00046     {"PM_FPU0_SINGLE", -1}
00047     ,
00048     {"PM_FPU0_STALL3", -1}
00049     ,
00050     {"PM_FPU0_STF", -1}
00051     ,
00052     {"PM_FPU1_ALL", -1}
00053     ,
00054     {"PM_FPU1_DENORM", -1}
00055     ,
00056     {"PM_FPU1_FDIV", -1}
00057     ,
00058     {"PM_FPU1_FMA", -1}
00059     ,
00060     {"PM_FPU1_FSQRT", -1}
00061     ,
00062     {"PM_FPU1_FULL_CYC", -1}
00063     ,
00064     {"PM_FPU1_SINGLE", -1}
00065     ,
00066     {"PM_FPU1_STALL3", -1}
00067     ,
00068     {"PM_FPU1_STF", -1}
00069     ,
00070     {"PM_FPU_DENORM", -1}
00071     ,
00072     {"PM_FPU_FDIV", -1}
00073     ,
00074     {"PM_GCT_EMPTY_CYC", -1}
00075     ,
00076     {"PM_GCT_FULL_CYC", -1}
00077     ,
00078     {"PM_GRP_BR_MPRED", -1}
00079     ,
00080     {"PM_GRP_BR_REDIR", -1}
00081     ,
00082     {"PM_GRP_DISP_REJECT", -1}
00083     ,
00084     {"PM_GRP_DISP_VALID", -1}
00085     ,
00086     {"PM_IC_PREF_INSTALL", -1}
00087     ,
00088     {"PM_IC_PREF_REQ", -1}
00089     ,
00090     {"PM_IERAT_XLATE_WR", -1}
00091     ,
00092     {"PM_INST_CMPL", -1}
00093     ,
00094     {"PM_INST_DISP", -1}
00095     ,
00096     {"PM_INST_FROM_L1", -1}
00097     ,
00098     {"PM_INST_FROM_L2", -1}
00099     ,
00100     {"PM_ISLB_MISS", -1}
00101     ,
00102     {"PM_ITLB_MISS", -1}
00103     ,
00104     {"PM_LARX_LSU0", -1}
00105     ,
00106     {"PM_LR_CTR_MAP_FULL_CYC", -1}
00107     ,
00108     {"PM_LSU0_DERAT_MISS", -1}
00109     ,
00110     {"PM_LSU0_FLUSH_LRQ", -1}
00111     ,
00112     {"PM_LSU0_FLUSH_SRQ", -1}
00113     ,
00114     {"PM_LSU0_FLUSH_ULD", -1}
00115     ,
00116     {"PM_LSU0_FLUSH_UST", -1}
00117     ,
00118     {"PM_LSU0_REJECT_ERAT_MISS", -1}
00119     ,
00120     {"PM_LSU0_REJECT_LMQ_FULL", -1}
00121     ,
00122     {"PM_LSU0_REJECT_RELOAD_CDF", -1}
00123     ,
00124     {"PM_LSU0_REJECT_SRQ", -1}
00125     ,
00126     {"PM_LSU0_SRQ_STFWD", -1}
00127     ,
00128     {"PM_LSU1_DERAT_MISS", -1}
00129     ,
00130     {"PM_LSU1_FLUSH_LRQ", -1}
00131     ,
00132     {"PM_LSU1_FLUSH_SRQ", -1}
00133     ,
00134     {"PM_LSU1_FLUSH_ULD", -1}
00135     ,
00136     {"PM_LSU1_FLUSH_UST", -1}
00137     ,
00138     {"PM_LSU1_REJECT_ERAT_MISS", -1}
00139     ,
00140     {"PM_LSU1_REJECT_LMQ_FULL", -1}
00141     ,
00142     {"PM_LSU1_REJECT_RELOAD_CDF", -1}
00143     ,
00144     {"PM_LSU1_REJECT_SRQ", -1}
00145     ,
00146     {"PM_LSU1_SRQ_STFWD", -1}
00147     ,
00148     {"PM_LSU_FLUSH_ULD", -1}
00149     ,
00150     {"PM_LSU_LRQ_S0_ALLOC", -1}
00151     ,
00152     {"PM_LSU_LRQ_S0_VALID", -1}
00153     ,
00154     {"PM_LSU_REJECT_SRQ", -1}
00155     ,
00156     {"PM_LSU_SRQ_S0_ALLOC", -1}
00157     ,
00158     {"PM_LSU_SRQ_S0_VALID", -1}
00159     ,
00160     {"PM_LSU_SRQ_STFWD", -1}
00161     ,
00162     {"PM_MRK_DATA_FROM_L2", -1}
00163     ,
00164     {"PM_MRK_GRP_DISP", -1}
00165     ,
00166     {"PM_MRK_IMR_RELOAD", -1}
00167     ,
00168     {"PM_MRK_LD_MISS_L1", -1}
00169     ,
00170     {"PM_MRK_LD_MISS_L1_LSU0", -1}
00171     ,
00172     {"PM_MRK_LD_MISS_L1_LSU1", -1}
00173     ,
00174     {"PM_MRK_STCX_FAIL", -1}
00175     ,
00176     {"PM_MRK_ST_CMPL", -1}
00177     ,
00178     {"PM_MRK_ST_MISS_L1", -1}
00179     ,
00180     {"PM_PMC8_OVERFLOW", -1}
00181     ,
00182     {"PM_RUN_CYC", -1}
00183     ,
00184     {"PM_SNOOP_TLBIE", -1}
00185     ,
00186     {"PM_STCX_FAIL", -1}
00187     ,
00188     {"PM_STCX_PASS", -1}
00189     ,
00190     {"PM_ST_MISS_L1", -1}
00191     ,
00192     {"PM_SUSPENDED", -1}
00193     ,
00194     {"PM_XER_MAP_FULL_CYC", -1}
00195     ,
00196     {"PM_FPU_FMA", -1}
00197     ,
00198     {"PM_FPU_STALL3", -1}
00199     ,
00200     {"PM_GCT_EMPTY_SRQ_FULL", -1}
00201     ,
00202     {"PM_GRP_DISP", -1}
00203     ,
00204     {"PM_INST_FROM_MEM", -1}
00205     ,
00206     {"PM_LSU_FLUSH_UST", -1}
00207     ,
00208     {"PM_LSU_LMQ_SRQ_EMPTY_CYC", -1}
00209     ,
00210     {"PM_LSU_REJECT_LMQ_FULL", -1}
00211     ,
00212     {"PM_MRK_BRU_FIN", -1}
00213     ,
00214     {"PM_PMC1_OVERFLOW", -1}
00215     ,
00216     {"PM_THRESH_TIMEO", -1}
00217     ,
00218     {"PM_WORK_HELD", -1}
00219     ,
00220     {"PM_BR_ISSUED", -1}
00221     ,
00222     {"PM_BR_MPRED_CR", -1}
00223     ,
00224     {"PM_BR_MPRED_TA", -1}
00225     ,
00226     {"PM_CRQ_FULL_CYC", -1}
00227     ,
00228     {"PM_DATA_FROM_MEM", -1}
00229     ,
00230     {"PM_DC_INV_L2", -1}
00231     ,
00232     {"PM_DC_PREF_OUT_OF_STREAMS", -1}
00233     ,
00234     {"PM_DC_PREF_STREAM_ALLOC", -1}
00235     ,
00236     {"PM_EE_OFF", -1}
00237     ,
00238     {"PM_EE_OFF_EXT_INT", -1}
00239     ,
00240     {"PM_FLUSH_BR_MPRED", -1}
00241     ,
00242     {"PM_FLUSH_LSU_BR_MPRED", -1}
00243     ,
00244     {"PM_FPU0_FEST", -1}
00245     ,
00246     {"PM_FPU0_FIN", -1}
00247     ,
00248     {"PM_FPU0_FMOV_FEST", -1}
00249     ,
00250     {"PM_FPU0_FPSCR", -1}
00251     ,
00252     {"PM_FPU0_FRSP_FCONV", -1}
00253     ,
00254     {"PM_FPU1_FEST", -1}
00255     ,
00256     {"PM_FPU1_FIN", -1}
00257     ,
00258     {"PM_FPU1_FMOV_FEST", -1}
00259     ,
00260     {"PM_FPU1_FRSP_FCONV", -1}
00261     ,
00262     {"PM_FPU_FEST", -1}
00263     ,
00264     {"PM_FXLS0_FULL_CYC", -1}
00265     ,
00266     {"PM_FXLS1_FULL_CYC", -1}
00267     ,
00268     {"PM_FXU0_FIN", -1}
00269     ,
00270     {"PM_FXU1_FIN", -1}
00271     ,
00272     {"PM_FXU_FIN", -1}
00273     ,
00274     {"PM_GPR_MAP_FULL_CYC", -1}
00275     ,
00276     {"PM_GRP_DISP_BLK_SB_CYC", -1}
00277     ,
00278     {"PM_HV_CYC", -1}
00279     ,
00280     {"PM_INST_FROM_PREF", -1}
00281     ,
00282     {"PM_L1_DCACHE_RELOAD_VALID", -1}
00283     ,
00284     {"PM_L1_PREF", -1}
00285     ,
00286     {"PM_L1_WRITE_CYC", -1}
00287     ,
00288     {"PM_L2_PREF", -1}
00289     ,
00290     {"PM_LD_MISS_L1", -1}
00291     ,
00292     {"PM_LD_MISS_L1_LSU0", -1}
00293     ,
00294     {"PM_LD_MISS_L1_LSU1", -1}
00295     ,
00296     {"PM_LD_REF_L1_LSU0", -1}
00297     ,
00298     {"PM_LD_REF_L1_LSU1", -1}
00299     ,
00300     {"PM_LSU0_LDF", -1}
00301     ,
00302     {"PM_LSU1_LDF", -1}
00303     ,
00304     {"PM_LSU_FLUSH", -1}
00305     ,
00306     {"PM_LSU_LMQ_FULL_CYC", -1}
00307     ,
00308     {"PM_LSU_LMQ_LHR_MERGE", -1}
00309     ,
00310     {"PM_LSU_LMQ_S0_ALLOC", -1}
00311     ,
00312     {"PM_LSU_LMQ_S0_VALID", -1}
00313     ,
00314     {"PM_LSU_LRQ_FULL_CYC", -1}
00315     ,
00316     {"PM_LSU_SRQ_FULL_CYC", -1}
00317     ,
00318     {"PM_LSU_SRQ_SYNC_CYC", -1}
00319     ,
00320     {"PM_MRK_DATA_FROM_MEM", -1}
00321     ,
00322     {"PM_MRK_L1_RELOAD_VALID", -1}
00323     ,
00324     {"PM_MRK_LSU0_FLUSH_LRQ", -1}
00325     ,
00326     {"PM_MRK_LSU0_FLUSH_SRQ", -1}
00327     ,
00328     {"PM_MRK_LSU0_FLUSH_ULD", -1}
00329     ,
00330     {"PM_MRK_LSU0_FLUSH_UST", -1}
00331     ,
00332     {"PM_MRK_LSU1_FLUSH_LRQ", -1}
00333     ,
00334     {"PM_MRK_LSU1_FLUSH_SRQ", -1}
00335     ,
00336     {"PM_MRK_LSU1_FLUSH_ULD", -1}
00337     ,
00338     {"PM_MRK_LSU1_FLUSH_UST", -1}
00339     ,
00340     {"PM_MRK_LSU_SRQ_INST_VALID", -1}
00341     ,
00342     {"PM_MRK_ST_CMPL_INT", -1}
00343     ,
00344     {"PM_MRK_VMX_FIN", -1}
00345     ,
00346     {"PM_PMC2_OVERFLOW", -1}
00347     ,
00348     {"PM_STOP_COMPLETION", -1}
00349     ,
00350     {"PM_ST_REF_L1_LSU0", -1}
00351     ,
00352     {"PM_ST_REF_L1_LSU1", -1}
00353     ,
00354     {"PM_0INST_FETCH", -1}
00355     ,
00356     {"PM_FPU_FIN", -1}
00357     ,
00358     {"PM_FXU1_BUSY_FXU0_IDLE", -1}
00359     ,
00360     {"PM_LSU_SRQ_EMPTY_CYC", -1}
00361     ,
00362     {"PM_MRK_CRU_FIN", -1}
00363     ,
00364     {"PM_MRK_GRP_CMPL", -1}
00365     ,
00366     {"PM_PMC3_OVERFLOW", -1}
00367     ,
00368     {"PM_1PLUS_PPC_CMPL", -1}
00369     ,
00370     {"PM_DATA_FROM_L25_SHR", -1}
00371     ,
00372     {"PM_FPU_ALL", -1}
00373     ,
00374     {"PM_FPU_SINGLE", -1}
00375     ,
00376     {"PM_FXU_IDLE", -1}
00377     ,
00378     {"PM_GRP_DISP_SUCCESS", -1}
00379     ,
00380     {"PM_GRP_MRK", -1}
00381     ,
00382     {"PM_INST_FROM_L25_SHR", -1}
00383     ,
00384     {"PM_LSU_FLUSH_SRQ", -1}
00385     ,
00386     {"PM_LSU_REJECT_ERAT_MISS", -1}
00387     ,
00388     {"PM_MRK_DATA_FROM_L25_SHR", -1}
00389     ,
00390     {"PM_MRK_GRP_TIMEO", -1}
00391     ,
00392     {"PM_PMC4_OVERFLOW", -1}
00393     ,
00394     {"PM_DATA_FROM_L25_MOD", -1}
00395     ,
00396     {"PM_FPU_FSQRT", -1}
00397     ,
00398     {"PM_FPU_STF", -1}
00399     ,
00400     {"PM_FXU_BUSY", -1}
00401     ,
00402     {"PM_INST_FROM_L25_MOD", -1}
00403     ,
00404     {"PM_LSU_DERAT_MISS", -1}
00405     ,
00406     {"PM_LSU_FLUSH_LRQ", -1}
00407     ,
00408     {"PM_LSU_REJECT_RELOAD_CDF", -1}
00409     ,
00410     {"PM_MRK_DATA_FROM_L25_MOD", -1}
00411     ,
00412     {"PM_MRK_FXU_FIN", -1}
00413     ,
00414     {"PM_MRK_GRP_ISSUED", -1}
00415     ,
00416     {"PM_MRK_ST_GPS", -1}
00417     ,
00418     {"PM_PMC5_OVERFLOW", -1}
00419     ,
00420     {"PM_FPU_FRSP_FCONV", -1}
00421     ,
00422     {"PM_FXU0_BUSY_FXU1_IDLE", -1}
00423     ,
00424     {"PM_GRP_CMPL", -1}
00425     ,
00426     {"PM_MRK_FPU_FIN", -1}
00427     ,
00428     {"PM_MRK_INST_FIN", -1}
00429     ,
00430     {"PM_PMC6_OVERFLOW", -1}
00431     ,
00432     {"PM_ST_REF_L1", -1}
00433     ,
00434     {"PM_EXT_INT", -1}
00435     ,
00436     {"PM_FPU_FMOV_FEST", -1}
00437     ,
00438     {"PM_LD_REF_L1", -1}
00439     ,
00440     {"PM_LSU_LDF", -1}
00441     ,
00442     {"PM_MRK_LSU_FIN", -1}
00443     ,
00444     {"PM_PMC7_OVERFLOW", -1}
00445     ,
00446     {"PM_TB_BIT_TRANS", -1}
00447 };